Secure Realtime Quick-to-Market Project (SRQ-to-M

Synaptic Labs' Secure Real-time Quick-to-Market computing proposal is designed to rapidly improve existing multi-core computer architectures so they can achieve significantly better real-time performance and/or higher information security assurances, lower risk, and easier safety and/or security certification.  

SRQ-to-M is ideal for safety-critical, security-critical and mixed-criticality cyber-physical systems. 

Synaptic Labs' SRQ-to-M is designed to be suitable for all mainstream CPU instruction sets, giving it extremely broad global market potential. SRQ-to-M will support from 2 to 16 standard low-area processor cores as favoured by the real-time community. SRQ-to-M can also mix-and-match time analyzable and high-performance cores in one multi-core chip.   SRQ-to-M does NOT replace or compete against any existing CPU, Cache or Peripheral module.  Furthermore, SRQ-to-M does NOT modify the CPU, Cache or Network on Chip technologies.  Rather, it shows how project designers and vendors can quickly apply, or make minor adjustments to improve, existing field proven IP to achieve superior results for themselves and their customers in real-time systems. 

SRQ-to-M will significantly improve multi-core worst-case and also multi-core average-case performance.  It achieves this in part by controlling or eliminating the root causes of timing interference at the hardware level, in a way that is highly desired for security, worst case execution time analysis, multi-core average case and worst case performance.  Addressing the root causes of timing interference in hardware results in solutions that offer higher levels of safety and security assurance, are better positioned to satisfy evolving standards and to reduce after sales service claims, and to make ongoing standards certification compliance easier. This all contributes towards significantly lower non-recurring-engineering (NRE) costs for developers.

A quad-core SRQ-to-M inplementation will run 2 hard real-time tasks with industry leading performance, in a static time analysable way, while concurrently running other arbitrary tasks of lesser criticality. SRQ-to-M fine tunes existing COTS designs to satisfy unmet market needs, unlocking 4x more peak computing power in quad-core hard real-time applications (scales to 16 cores).  

In our view, when implemented, SRQ-to-M will provide developers with the best platform in the market for developing mixed criticality systems.    

Problem statement and market size

According to a report by PROARTIS:

"The market for Critical Real-Time Embedded Systems (CRTES), which among others includes the avionics and automotive sectors, is experiencing an unprecedented growth, and is expected to continue to steadily grow for the foreseeable future." ...

"The competition on functional value, measured in terms of application services delivered per unit of product faces CRTES industry with rising demands for greater performance, increased computing power, and stricter cost-containment. The latter factor puts pressure on the reduction in the number of processing units and ECUs used in the system, to which industry responds by looking at more powerful processors, with aggressive hardware acceleration features like caches and deep memory hierarchies.

In this evolving scenario, it must be acknowledged that the industrial application of current WCET analysis techniques, which accounts for a significant proportion of total verification and validation time and cost of system production, yields far from perfect results. IBM has for example found that 50% of the warranty costs in cars are related to electronics and their embedded software, and that 30% of those costs are related to timing flaws. These instances of incorrect operation cost industry billions of Euros annually [See article here]."

Synaptic Labs' SRQ-to-M proposal (technical)

Synaptic Labs is working on hardening existing soft core processors (such as ARM9 and LEON3/4) and computer subsystems to significantly improve their worst case execution time predictability in real-time multi-tasking environments and to secure them against certain classes of covert channel attack.  The goal of SRQ-to-M is to propose a small, limited subset of changes to existing multi-core platforms that can significantly improve their real-time performance. 

From an operating system perspective, you could think of this project as creating a new family member of the ARM or SPARC family of processors. The user and privileged instruction sets will be unmodified.  There are no software changes necessary to support context swapping.  Existing on-chip networks (such as AMBA AHB BUS) can be used without modification.  No adjustments are required to the implementation of existing L1 or L2 cache modules.  Existing memory controllers can be used without modifications.  There are no changes needed to peripherals, etc. 

Very minor changes will be required to real-time operating system code base and Type-1 hypervisors to support our proposed SRQ-to-M platform. Synaptic Labs is drawing together RTOS and CPU vendors to collaborate on the project to ensure the SRQ-to-M product specifications are optimised (with the lowest possible integration costs) for collaborating CPU and RTOS products, while maintaining the full functionality.  As with all real-time projects, real-time software must be adapted to each multi-core platform.  SRQ-to-M is designed to provide developers a significantly better multi-core platform for developing, maintaining and certifying real-time applications on multi-core platforms, reducing or eliminating known problems on mainstream multi-core platforms. 

The fundamental problem with today's processors (non-technical)

Brian Snow was a former Technical Director of the U.S. National Security Agency for 12 years.  Brian Snow asserts in his publication "We Need Assurance!" (and elsewhere) that one of the fundamental causes of security problems in ICT is that most computers have been designed first and foremost to SHARE resources (CPU, Memory) between tasks to achieve better (average-case) performance and to reduce hardware costs.  

Brian Snow says it is very hard to achieve security on today's computing systems which are designed in the above way.  The reason is because in the security realm the goal is to SEPARATE tasks from each other, to keep each one independent and secure while "keeping the bad guys away from the good guys' stuff!".

Not surprisingly, this "SEPARATION" problem is made significantly worse in the shift from single core to multi-core computing systems. In high-assurance mixed-criticality systems the interference due to multiple cores is so bad in today's mainstream systems, that the designers temporarily disable all but one core to make the remaining sources of interference manageable when performing time critical tasks.

Similar problems exist with real-time systems.  Today's computing systems are designed to share resources between many competing tasks.  Today's computers are optimised to increase the total amount of work completed by the tasks in the systems, with little concern for a task's deadlines.  In real-time systems, the goal is to ensure every time critical task meets it's deadline, every time, in an orderly manner.  To do this, one task should not interfere (in an uncontrolled way) with the time it takes for another task to execute.  That is, we need to SEPERATE tasks from each other. 

And this brings us back to the problem of trying to use today's computers in high assurance safety and security applications.  Today's real-time and security operating systems are imposing a "separation" model on computing devices that are heavily biased by design towards a "sharing" model.  This mismatch results in tasks interacting with each other in ways that violate important safety and security requirements (for example see: non-interference and side-channel attack). 

Click on the accordion entry directly below to read how Synaptic Labs' SRQ-to-M project cost effectively addresses these problem in the hardware in a way that improves overall system performance.

Synaptic Labs' SRQ-to-M will address the fundamental problems (non-technical)

The fundamental problems faced by real-time operating systems, high assurance operating systems, and hypervisors stem from the fact that they are trying to seperate tasks and virtual machines from each other on computing devices that have been designed first and foremost to SHARE resources.

Synaptic Labs' safe and secure computing projects address the heart of this problem by enhancing existing computing architectures to employ a seperation paradigm in the central processing unit and supporting sub systems, while achieve excellent performance.  Synaptic Labs' Secure Real-time Revolution computer design comprehensively eliminates timing interference, providing the ultimate platform for real-time development.  Synaptic Labs' Secure Real-time Quick-to-Market platform draws on some techniques used in SRRevolution, with the primary focus of acheiving an "evolutionary" improvement and making this available to the community in less than 12 months.  SRQ-to-M focusses predominantly on rapidly delivering new real-time capabilities to all tasks in cyber-physical systems.  

SRQ-to-M is also designed to control timing channels and covert timing channels for a small number of tasks while permitting peripherals and other tasks to serviced in parallel; a task that cannot be performed by conventional multi-core platforms such as the European Space Agency's quad-core Next Generation Microprocessor (NGMP) architecture.  (By comparison, Synaptic Labs' SRRevolution, which we plan to be develop after SRQ-to-M, will be able to control timing and covert timing channels for all tasks, on all cores, all the time!)  

Synaptic Labs' SRQ-to-M improves both ACET and WCET performance (technical)

Mainstream multi-core systems share hardware resources to reduce cost. However, if not well managed, competition for shared resources can result in significant reductions in multi-core performance.

Synaptic Labs' SRQ-to-M design proposes changes to mainstream multi-core systems in simple ways that results in a significant reduction in contention when accessing shared resources. This reduction in contention results in significant performance improvements when executing concurrent general purpose and real-time tasks in mixed criticality systems.

Synaptic Labs' SRQ-to-M is a better multi-core environment for WCET analysis (technical)

Hard real-time systems require the ability to accurately predict the worst-case execution time (WCET) of a task. World-leading WCET analysis tools make certain assumptions about the operating environment of the task (e.g. No interrupts, no preemptions, no contention for shared resources on the processor bus, ...). For hard real-time tasks, this type of environment can be achieved in today's multi-core environments by disabling all but 1 processor core and all other peripherals; effectively temporarily creating a single core computer with no peripherals. In contrast, a quad-core implementation of SRQ-to-M can achieve this nearly perfect "single core equivalent" operating environment for a hard real-time task while permitting 2 other cores to actively service peripherals and perform other tasks at full speed. This capability provides significant performance gains to applications over conventional multi-core designs.

Synaptic Labs' SRQ-to-M design is widely complementary

Synaptic Labs' Secure Real-time Quick-to-Market:

  • Is designed to be suitable for all mainstream CPU instruction sets, devices and operating systems, giving it extremely broad global market potential;
  • Will enhance existing computing architectures to provide new time seperation / non-interference capabilities between tasks and/or virtual machines for existing real time operating systems and Type-1 hypervisors. 
  • Designed to be complementary and welcomed by all software Type-1 hypervisor products which have a history of rapidly taking up new hardware virtualisation technologies;
  • Is designed from the ground up as a real-time project;
  • Is designed from the ground up as an information security project.

Support and benefits for real-time systems (non-technical)

Real time computing systems are deployed across a very wide range of industries globally, including aerospace and defense, automobiles, mobile phones and many more.   Unfortunately, many of the modern computing performance gains made possible by the combination of pipelining and caching are difficult to control in single-core real time systems.  This real-time problem is made several times worse when today's modern CPU cores are used in multi-core systems. 

In the real-time industry, similar to the security industry, assurance of correct and predictable behavior takes precedence over (average case) performance.  Real-time systems which control physical processes (airplanes, space craft, cars, power stations, industrial control systems) rely on the ability to predict how long a task will take to execute, that is, the "worst-case execution time" (WCET).  

It is well known that modern processor architectures (ARM, TriCore, Power) use various techniques to increase the total amount of work done by improving the "average case execution time" (ACET).   Unfortunately these basic ACET techniques become increasing unpredictable when there is more than one task/Virtual Machine Instance competing for the same resources.  Increasing the number of active cores in the system severely exasperates this problem.  To quote Benoit Triquet from Airbus: "Airbus has ... found very few multicore chips that can ever hope to be useable for avionics" (2012).

Support for Linux, FreeBSD and Solaris

Synaptic Labs is collaborating with RTOS vendors that provide Type-1 (bare-metal) hypervisor.  Synaptic Labs'  Secure Real-time Quick-to-Market architecture is being designed to enhance RTOS vendor products that offer field-proven Hypervisors capable of running the above operating systems.  The goal is to allow operating systems such as Linux or Solaris to run efficiently, without any (or very little) modifications, on existing Hyprevisors running on existing real-time operating systems on processors that have been enhanced using our SRQ-to-M technologies.  

Support for Java

 Java "compatible" runtime environments provided by various third parties are available for several real-time operating systems that can in principle run on SRQ-to-M.  Synaptic Labs' will target full Sun Java support on the SRRevolution platform and TruSIP.   

Support for Android, Windows CE and iOS

Mobile phones, PDA's and Tablets are all example of embedded micro environments with a relatively small number of peripherals that are fixed at point of manufacture.  Synaptic Labs' SRQ-to-M is being targeted for use in these types of environments.

The Android operating systems is based on Linux.  The Android operating systems is supported by several Hypervisors offered by leading RTOS vendors.  From a technical perspective, it should be relatively easy for Synaptic Labs' SRQ-to-M to support the Android operating system on an ARM or MIPS processor using existing RTOS vendor's Hypervisors.

Windows CE for embedded and mobile devices supports ARM, MIPS and Intel (x86) chip sets.  VMware have a hypervisor that runs Windows CE and Android on the same computing device.   We anticipate that the easiest way to support Windows CE will be for Synaptic Labs to collaborate with VMware on an ARM or MIPS processor with or without Microsoft's support.  (Microsoft Windows CE is an entirely different operating system to the desktop and server versions of the Microsoft Windows Family.)

The Apple iOS operating system is based on a modified FreeBSD.  The Apple iOS which runs on the ARM processor has not been released to the public.  Achieving a seamless, high-performance, iOS experience will require some collaboration between Synaptic Labs, Apple and ARM.

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The SRQ-to-M project is part of Synaptic Labs' global inclusive cyber security ecosystem, where each part can stand alone to resolve key needs

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GBC1 SLL-Logo_150  A Collaborative Project co founded by
PaceIT & The Gozo Business Chamber and
Synaptic Laboratories Ltd

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Eco-Gozo – a Better Gozo Action Plan 2010 – 2012
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